Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B420F2048GL120 /SDIO /CLOCKCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLOCKCTRL

31282724232019161512118743000000000000000000000000000000000000000000 (INTCLKEN)INTCLKEN0 (INTCLKSTABLE)INTCLKSTABLE0 (SDCLKEN)SDCLKEN0 (CLKGENSEL)CLKGENSEL0UPPSDCLKFRE0 (NODIVISION)SDCLKFREQSEL0DATTOUTCNTVAL0 (SFTRSTA)SFTRSTA0 (SFTRSTCMD)SFTRSTCMD0 (SFTRSTDAT)SFTRSTDAT

SDCLKFREQSEL=NODIVISION

Description

Clock Control, Timeout Control and Software Register

Fields

INTCLKEN

Internal Clock Enable

INTCLKSTABLE

Internal Clock Stable

SDCLKEN

SDIO_CLK Pin Clock Enable

CLKGENSEL

Clock Generator Select

UPPSDCLKFRE

Upper Bits of SD_CLK Frequency Select

SDCLKFREQSEL

SD_CLK Frequency Select

0 (NODIVISION): undefined

DATTOUTCNTVAL

Data Timeout Counter Value

SFTRSTA

Software Reset for All

SFTRSTCMD

Software Reset for CMD Line

SFTRSTDAT

Software Reset for DAT Line

Links

() ()